Xilinx KCU105 User Manual page 43

• During bridge register initialization:
Bridge base low (0x210) is programmed to (BAR0 + 0x8000).
°
Bridge Control register (0x208) is programmed to set the bridge size and enable
°
translation.
• After bridge translation has been enabled, ingress registers can be accessed with
bridge base + 0x800.
• The read and write request size for Master AXI read and write transactions is
programmed to be 256B (cfg_axi_master register at offset 0x08 from [BAR0 +
0x8000]).
Expresso DMA
Key features of Expresso DMA are:
• High-performance scatter gather DMA designed to achieve full bandwidth of AXI and
PCIe
• Separate source and destination scatter-gather queues with separate source and
destination DMA completion status queues
• DMA channels merge the source and destination scatter gather information
DMA Operation
In this section, Q is short for queue.
Note:
The Expresso DMA has four queues per channel:
• SRC-Q provides data buffer source information and corresponding STAS-Q which
indicates SRC-Q processing completion by DMA
• DST-Q provides destination buffer information and corresponding STAD-Q which
indicates DST-Q processing completion by DMA
The queue element layout is depicted in
X-Ref Target - Figure 5-2
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Figure
Figure 5-2: SGL Queue Element Structure
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5-2.
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