Xilinx KCU105 User Manual page 53

Streaming Generator/Checker
The design has a 128-bit streaming interface-based traffic generator and checker
(Generator/Checker) module. It operates at a 200 MHz user clock derived from the PCIe
interface. Hardware SGL Prepare module interfaces between this block and the Northwest
Logic DMA block in the data plane. The traffic generator and checker interface follow
AXI4-Stream protocol. The packet length is configurable through the control interface.
Refer to Appendix C, Register Space
The traffic Generator/Checker module can be used in three different modes: a loopback
mode, a data checker mode, and a data generator mode. The module enables specific
functions depending on the configuration options selected. On the transmit path, the data
checker verifies the data transmitted from the host system through the packet DMA. On the
receive path, data can be sourced either by the data generator or transmit data from the
host system can be looped back to itself. Based on user inputs, the software driver programs
the core to enable the checker, generator, or loopback mode of operation. The data
received and transmitted by the module is divided into packets. The first two bytes of each
packet define the length of the packet. All other bytes carry the tag, which is the sequence
number of the packet.
Packet Checker
If the Enable Checker bit is set (registers are defined in
as data is valid on the DMA transmit channel (S2C) through the hardware SGL block, each
data byte received is checked against a pre-decided data pattern. If there is a mismatch
during a comparison, the data mismatch signal is asserted. This status is reflected back in a
register which can be read by the software driver through the control plane.
Packet Generator
If the Enable Generator bit is set (registers are defined in
data produced by the generator is passed to the receive channel of the DMA (C2S) through
the hardware SGL block. The data from the generator also follows the same pre-decided
data pattern as the packet checker.
Power and Temperature Monitoring
The design uses a SYSMON block (17 channel, 200 ksps) to provide system power and die
temperature monitoring capabilities. The block provides analog-to-digital conversion and
monitoring capabilities. It enables reading of voltage and current on different power supply
rails (supported on the KCU105 board) which are then used to calculate power.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
for register map details of Generator/Checker.
www.xilinx.com
Appendix C, Register Space), as soon
Appendix C, Register
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