Xilinx KCU105 User Manual page 52

A block diagram of the C2S Prepare block is shown in
X-Ref Target - Figure 5-9
The C2S Prepare module consists of the following:
• Block RAM controller
• True dual port block RAM
• Custom logic for stream to block RAM native interface conversion
• Hardware SGL Prepare block
The C2S Prepare block has a true dual port block memory capable of storing up to eight
buffers, 4096 bytes each. One side of the block RAM is accessed by DMA through the AXI
MM interface to read buffers, whereas the other side of the block RAM is accessed by
custom logic to update the data buffers.
Custom logic converts the incoming stream data into block RAM native interface and
updates the block RAM buffer one after the other, depending on empty buffer availability.
The hardware SGL Prepare block prepares an SGL element whenever it sees an end of packet
or with the minimum buffer size update (4096 bytes).
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Figure 5-9: C2S Prepare Block Diagram
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Figure 5-9.
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