Synthesis And Implementation; Design Flow Environment - Xilinx ML40 Series User Manual

Edk processor reference design

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Table of Contents

Table 2-1: IP Cores in the ML40x Embedded Processor Reference System

Notes:

1. Modified to reduce power consumption.

2. Modified to use alternate boundary scan (BSCAN) primitive required for early Virtex-4 engineering

Synthesis and Implementation

The ML40x Embedded Processor Reference System can be synthesized and placed/routed

into a Virtex-4 FPGA under the EDK tools. A basic set of timing constraints for the design

is provided to allow the design to go through place-and-route.

Design Flow Environment

The EDK provides an environment to help manage the design flow for the ML40x

Embedded Processor Reference System including synthesis, implementation, and

software compilation. EDK offers a GUI or command line interface to run these tools as

part of the design flow. Consult the EDK documentation for more information.

ML40x EDK Processor Reference Design

UG082 (v5.0) June 30, 2006

Hardware IP

opb_ethernet

opb_gpio

opb_iic (PPC405 systems)

opb_intc

opb_mdm

(MicroBlaze systems)

opb_ps2_dual_ref

opb_sysace

opb_uart16550

opb_v20

opb2dcr_bridge

opb2plb_bridge

(MicroBlaze systems)

plb_bram_if_cntlr

(PPC405 systems)

plb_ddr

plb_tft_cntlr_ref

plb_v34

plb2opb_bridge

(PPC405 systems)

ppc405_virtex4

(PPC405 systems)

proc_sys_reset

sample (ES) devices.

www.xilinx.com

Synthesis and Implementation

Version

1.02.a

3.01.b

1.01.d

1.00.c

2.01.a (ML401)

2.00.a (ML402/ML403)

1.00.a

1.00.c

1.00.d

1.10.c

1.00.b

1.00.c

1.00.b

1.11.a

1.00.c

1.02.a

1.01.a

1.00.a

Source

EDK Installation

(2)

pcores Directory

Local

EDK Installation

Local

pcores Directory

EDK Installation

pcores Directory

Local

EDK Installation

Table of Contents

Synthesis And Implementation; Design Flow Environment - Xilinx ML40 Series User Manual

Synthesis and Implementation

Design Flow Environment

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