Xilinx KCU105 User Manual page 48

1. In the SGL allocation phase, the SGL submission logic requests the DMA SGL interface to
reserve the DMA shared memory-mapped interface for a particular AXI4-Stream
channel. The DMA SGL interface acknowledges the request with a Grant status.
2. After the allocation phase is over, the SGL element is fetched from the SGL preparation
logic and the SGL submission logic informs the hardware SGL preparation logic with a
SGL Done status.
The padding of additional fields in the SGL element is performed by the SGL padding logic
in the submission block. The SGL data that the preparation logic submits contains the fields
of the SGL element shown in
Table 5-4: Description of SGL Element by SGL Preparation Block
Field Name
ByteCount
Flags (per SRC/DST -
SGL description)
UserId
Buffer Address
Figure 5-7 shows the state diagram for the SGL submission finite state machine (FSM) that
reserves the SGL allocation interface and submits SGL elements based on the allocation
status.
The FSM arbitrates over the DMA channels in a round-robin order. The FSM checks for SGL
valid from a specific DMA channel and if sgl_available is not asserted, moves over to the
next channel. If the sgl_available signal is asserted, the FSM moves ahead, reserving the
DMA interface for the requesting channel. After the allocation phase is over, it submits the
elements with appropriate padding to the SGL allocation interface of the Expresso DMA.
The FSM embodies two timers:
• The first timer in the SGL allocation phase defines the wait time while waiting for the
DMA interface to issue a grant for the particular channel. If timeout occurs, the FSM
moves over to the next channel.
• The second timer waits on the acknowledgment from the DMA SGL interface while the
submission block submits the SGL elements to DMA. If a timeout occurs, the
submission block flags an error to the preparation logic.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Table 5-4.
Bit Position in sgl_data
[23:0]
[31:24]
[47:32]
[79:48] or [111:48]
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Description
DMA ByteCount based on the FIFO occupancy count
Populated as per flag definition in SRC/DST-SGL
User-defined information
Buffer Address
Would be reduced to 32 bits.
Keep option for 64-bit programmable to address
future needs.
64-bit addressing selected through attribute
64_BIT_ADDR_EN.
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