Xilinx KCU105 User Manual page 85

The depth of the FIFO in receive interface logic is decided based on the maximum length of
the frame to be buffered and the potential back-pressure imposed by the packet buffer. The
possible scenario of FIFO overflow occurs when the received frames are not drained out at
the required rate, in which case receive interface logic drops Ethernet frames. The logic also
takes care of cleanly dropping entire packets due to this local FIFO overflowing.
Address Filtering
Address filtering logic filters out a specific packet which is output from the XGEMAC receive
interface if the destination address of the packet does not match with the programmed
MAC address. A MAC address can be programmed by software using the register interface.
Address filtering logic does the following:
• Performs address filtering on the fly based on the MAC address programmed by
software
• Allows broadcast frames to pass through
• Allows all frames to pass through when Promiscuous mode is enabled
The receive interface state machine compares this address with the first 48 bits it receives
from the XGEMAC-RX interface during start of a new frame. If it finds a match, it writes the
packet to the receive FIFO in the receive interface; otherwise, the packet is dropped as it
comes out of the XGEMAC receive interface.
Rebuilding Hardware
A pre-built design script is provided for the user extension design which can be run to
generate a bitstream. The steps required to build the user extension design are described in
Chapter 4, Implementing and Simulating the
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Design.
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