Xilinx KCU105 User Manual page 51

S2C Prepare block has a true dual port block memory capable of storing up to eight buffers
of 4096 bytes each. One side of the block RAM is accessed by DMA through the AXI MM
interface to update buffers, whereas the other side of the block RAM is accessed by the read
engine to read the data buffers.
After reset, hardware SGL Prepare logic submits eight SGL elements to DMA about the
availability of eight buffers, 4096 bytes each. This logic monitors the AXI MM (from DMA)
write interface for minimum buffer data received (4096 bytes) or end of packet (one buffer
update event). With the buffer update event, it communicates to the read engine about the
data availability with buffer address, size, and EOP information for TLAST generation. After
the read engine fetches the buffer, Prepare logic submits a new SGL element to DMA
informing it of the availability of an empty buffer. To handle the latency of the
communication and for better performance, eight buffers are implemented in the design to
support pipelining.
The interface between the Prepare block and the read engine is listed in
Table 5-5: Description of Interface between the Prepare Block and the Read Engine
Signal
rd_addr
rd_bcnt
is_eop
rd_valid
rd_valid_rdy
rd_start
rd_start_rdy
rd_done
rd_done_ack
The Read engine module has two queues (read_valid and read_start) that are implemented
with FIFOs for handling multiple read requests from the preparation block. The Read engine
also handles the data conversion from the block RAM native interface to the AXI Streaming
interface.
C2S SGL Prepare logic handles the following:
• AXI block RAM is instantiated in the design to handle the DMA AXI MM read interface.
Data from the user application (beyond DMA) is buffered here temporarily. Each block
RAM can hold up to 4 KB of data (8 buffers of 4096 bytes each).
• After the data size reaches 4096 bytes or end of packet (tlast) occurs (whichever occurs
first), builds the SRC-SGL element and submits it to the corresponding DMA channel.
• Continues providing SRC_SGL elements as newer data keeps coming into block RAM.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Buffer starting address to read
Valid bytes in the buffer
End of packet information
Valid signal for read request
Read Valid acknowledgment from the read engine
Start signal for read request
Read Start acknowledgment from the read engine
Read completion signal from the read engine
Acknowledgment for Read completion signal
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