Xilinx KCU105 User Manual page 42

Endpoint Block for PCI Express
The Endpoint block for PCI Express is used in the following configuration:
• x8 Gen2 line rate (5 GT/s per lane per direction) where GT/s is GigaTransfers per second
• Three 64-bit BARs, 1 MB each
• MSI-X capability
See the LogiCORE IP UltraScale FPGAs Gen3 Integrated Block for PCI Express Product Guide
(PG156) [Ref 6]
DMA Bridge Core
The DMA bridge core includes an AXI-PCIe bridge and Expresso DMA in one netlist bundle.
See the Northwest Logic Expresso DMA Bridge Core website for more information
The IP netlist used in the reference design supports a fixed configuration where the number
Note:
of DMA channels and translation regions is fixed. For higher configurations of the IP, contact
Northwest Logic.
The Northwest Logic Expresso IP Core provided with the design is an evaluation version of the
Note:
IP. It times out in hardware after 12 hours. To obtain a full license of the IP, contact Northwest Logic.
AXI-PCIe Bridge
The AXI-PCIe bridge translates protocol to support transactions between the PCIe and AXI3
domains. It provides support for two ingress translation regions to convert PCIe
BAR-mapped transactions to AXI3 domain transactions.
Bridge Initialization
The AXI-PCIe bridge consumes transactions hitting BAR0 in the Endpoint.
• The bridge registers are accessible from BAR0 + 0x8000.
• During ingress translation initialization:
Single ingress translation is enabled (0x800).
°
Address translation is set up as shown in
°
For example, assume that the PCIe BAR2 physical address is 0x2E000000. A memory
read request targeted to address 0x2E000000 is translated to 0x44A00000.
Table 5-1: Address Translation Maps
Ingress Source Base
BAR2
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
for more information.
Ingress Destination Base
www.xilinx.com
Table 5-1.
0x44A00000
[Ref 7].
Aperture Size
1M
42
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