Xilinx KCU105 User Manual page 69

Setup Procedure for 2x10G Ethernet Design
Refer to Chapter 3, Bringing Up the
addition to this setup is to connect the SFP+ (Avago AFBR-709SMZ or AFBR-703SDZ)
back-to-back connection cable (10GGBLCX20) to both the SFP cages of the board (as shown
in Figure 5-14) and to connect both J6 and J7 jumpers on the board to enable SFP. Follow
the same procedure until FPGA configuration is done and PCIe Endpoint is discovered. The
BIT file to be used for this is
<working_dir>/kcu105_axis_dataplane/ready_to_test/trd03_2x10g_top.bit.
X-Ref Target - Figure 5-14
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Design, for steps on preliminary setup. The only
Figure 5-14: SFP+ Back-to-Back Connection
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