Xilinx KCU105 User Manual page 60

XDMA Driver Stack and Design
The XDMA driver provides APIs to application drivers. Most of these APIs require passing
the pointer to the SGL descriptor. The application driver has to create two SGL descriptors
for each channel it intends to use.
X-Ref Target - Figure 5-12
• API Logic: APIs exported to the application driver. This logic executes in the context of
the calling process. APIs can be invoked from process and bottom half context.
• Interrupt handling and post-processing logic: This logic performs post-processing
after an I/O buffer is submitted and Expresso DMA is done processing the buffer. For
source buffers, this logic takes affect when the data has been taken from source buffers
and copied into destination buffers. For destination buffers, this logic takes affect when
data is copied from source buffers into it. Post-processing logic performs cleanups after
a source or destination buffer is used (as source/sink of data) by DMA. Post-processing
logic invokes callbacks that might have been provided by the application driver.
• Bridge Initialization: The Expresso IP Core contains a bridge for protocol conversion
(AXI to PCIe and vice versa) which needs initialization. The details on bridge
initialization are documented under
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Figure 5-11
Figure 5-12: XDMA Driver Stack and Design
Bridge Initialization, page
www.xilinx.com
provides a functional block diagram.
42.
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