Xilinx KCU105 User Manual page 84

Ethernet MAC and PHY Subsystem
This block is the logic comprising packet FIFO for transmit, receive logic for optional
address filtering, 10G MAC, and 10GPCS-PMA (10GBASE-R) IP (see
FIFO handles the transmit requirement for 10G MAC where a packet once started cannot be
throttled in between. The maximum Ethernet frame size supported by the MAC is 16383
bytes (when jumbo is enabled), hence the packet FIFO should be deep enough to hold one
full frame of this size.
X-Ref Target - Figure 5-30
Receive Logic
The receive interface logic does the following:
• Receives incoming frames from 10G MAC and performs address filtering (if enabled to
do so)
• Based on packet status provided by 10G MAC-RX interface, decides whether to drop a
packet or pass it ahead to the system for further processing
The XGEMAC-RX interface does not allow back-pressure. That is, after a packet reception
has started, it completes the entire packet. The receive interface logic stores the incoming
frame in a local receive FIFO. This FIFO stores the data until it receives the entire frame. If
the frame is received without any error (indicated by tlast and tuser from the XGEMAC-RX
interface), it is passed ahead; otherwise it is dropped. The Ethernet packet length is read
from the receive statistics vector instead of implementing a separate counter in logic.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Figure 5-30: Ethernet MAC and PHY Subsystem
www.xilinx.com
Figure 5-30). The packet
UG920_c5_30_100214
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