Appendix C: Register Space; Generator And Checker Configuration Registers - Xilinx KCU105 User Manual

Register Space

Generator and Checker Configuration Registers

This section lists register map details for control and configuration of the Generator
Checker IP.
Table C-1: Enable Loopback Register (0x44A0_0000)
Bit Position Mode
31:1 Read only
0 R/W
Table C-2: Enable Generator Register (0x44A0_0004)
Bit Position Mode
31:1 Read only
0 R/W
Table C-3: Enable Checker Register (0x44A0_0008)
Bit Position Mode
31:1 Read only
0 R/W
Table C-4: Generator Length Register (0x44A0_000C)
Bit Position Mode
31:0 R/W
Table C-5: Checker Length Register (0x44A0_0010)
Bit Position Mode
31:0 R/W
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Default Value
Reserved
0
To enable Loopback mode. Value of 1 enables Loopback mode.
0
Default Value
Reserved
0
Enable traffic generator. Value of 1 enables traffic generator.
0
Default Value
Reserved
0
Enable traffic checker. Value of 1 enables traffic checker.
0
Default Value
Packet length to be generated in Generate mode.
0
Maximum supported size is 32 KB packets.
Default Value
Packet length to be checked in Checker mode.
0
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Appendix C
Description
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