Xilinx KCU105 User Manual page 50

This block handles one S2C and one C2S channel data transfer.
S2C SGL preparation logic handles these tasks:
• Uses an AXI memory-mapped block RAM per DMA channel to drain out data from
DMA. This data is used by the user application beyond DMA.
• Provides DST-SGL elements to corresponding DMA channels. Each element provides a
buffer size of 4096 bytes.
• Writes data to AXI MM block memory.
• Reads data from block RAM and converts the data to AXI Streaming before sending it
out.
• Keeps submitting DST-SGL elements (maximum of 8) per DMA channel as
corresponding buffers as the block RAM gets emptied.
Figure 5-8 depicts a block diagram of the S2C Prepare block.
X-Ref Target - Figure 5-8
The S2C Prepare module consists of following:
• Block RAM controller
• True dual port block RAM
• Read engine
• Hardware SGL Prepare block
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Figure 5-8: S2C Prepare Block Diagram
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