Xilinx KCU105 User Manual page 47

Refer to the
Note:
[Ref 1]
Interface
Because the i_sgl_* interface is a shared interface, a central logic for hardware SGL
submission is designed that performs these tasks:
• Handles the i_sgl_* protocol-based transfers.
• All user logic blocks submit the SGL elements along with identifiers like DMA channel,
byte count, and so on to this block.
• This block submits SGL elements to DMA in a round-robin mechanism for each DMA
channel.
Figure 5-6 depicts an interface between the hardware SGL Submit block and one of the
hardware SGL Prepare blocks. Each Prepare block interacts with Submit blocks with a
separate set of the mentioned interface signals.
X-Ref Target - Figure 5-6
Figure 5-6: Interface between Hardware SGL Prepare and Submit Blocks
Table 5-3: Hardware SGL Prepare and Submit Blocks Interface Signals Descriptions
Signal
sgl_available
sgl_data
sgl_done
sgl_error
Hardware SGL Submit Block
The SGL submit logic polls for the SGL available status from SGL preparation logic in a
round-robin fashion. The logic reserves one SGL element per AXI4-Stream DMA channel
and iterates over all the channels. The SGL submission logic communicates with the SGL
preparation logic using a ready-acknowledge handshaking mechanism. The handshaking
protocol for communicating with the DMA SGL interface happens in two phases:
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Northwest Logic Expresso DMA user guide
.
Indicates data on the sgl_data bus is a valid SGL element queued up for DMA.
Carries the required SGL element information.
Acknowledgment signal back from SGL submission logic when the sgl_data has been
submitted to DMA.
An error is signaled when either SGL allocation or SGL submission fails for that
channel.
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