Xilinx KCU105 User Manual page 21

6. Exit the BIOS and let the system boot.
7. On most systems, this gives a second reset on the PCIe connector, which should discover
the device during enumeration.
To know that the PCIe Endpoint is discovered, see
°
If the PCIe Endpoint is not discovered, reboot the system. Do not power off.
°
8. Check the status of the design by looking at the GPIO LEDs positioned at the top right
corner of the KCU105 board (see
from left to right indicates the following:
LED 3: ON if the link speed is Gen2, else flashing (Link Speed Error)
°
LED 2: ON if the lane width is x8, else flashing (Lane Width Error)
°
LED 1: Heartbeat LED, flashes if PCIe user clock is present
°
LED 0: ON if the PCIe link is UP
°
These LED numbers match the silkscreened numbers on the board.
Note:
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Figure 3-6). After FPGA configuration, the LED status
www.xilinx.com
Chapter 3: Bringing Up the Design
Check for PCIe Devices, page
Send Feedback
22.
21