Test The Reference Design - Xilinx KCU105 User Manual

Test the Reference Design

The control and monitoring GUI, shown in
FPGA die temperature, PCI Express Endpoint link status, host system initial flow control
credits, PCIe write and read throughput, and AXI throughput.
X-Ref Target - Figure 3-12
The following tests can be done through the main control and monitoring GUI:
• Data transfer from the host computer to the FPGA can be started by selecting System
to Card (S2C) test control mode, as shown in
• Data transfer from the FPGA to the host computer can be started by selecting Card to
System (C2S) test control mode, as shown in
• Data transfer from the FPGA to the host computer and vice versa can be started at the
same time by selecting both S2C and C2S test control modes together, as shown in
Figure 3-15.
Click Start to initiate the test. To stop the test, click Stop. (The Start button changes to Stop
after the test is initiated). The packet size for all the above modes can be between 64 bytes
and 32768 bytes.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Figure
Figure 3-12: Control & Monitoring GUI
www.xilinx.com
Chapter 3: Bringing Up the Design
3-12, provides information on power and
Figure 3-13.
Figure 3-14.
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