Xilinx KCU105 User Manual page 45

Status Updates
The status elements are updated only on end of packet (EOP) and not for every SGL
element. This section describes the status updates and use of the User Handle field.
Relationship between SRC-Q and STAS-Q
As depicted in
indicates EOP=1 with UserHandle=2. On EOP, DMA updates STAS-Q with UserHandle=2
which corresponds to the handle value in SRC-Q element with EOP=1. Similarly, packet-1
spans two elements, and in STAS-Q, the updated handle value corresponds to the EOP =1
element. This UserHandle mechanism allows software to associate the number of SRC-Q
elements with a corresponding STAS-Q update.
X-Ref Target - Figure 5-4
Relationship between DST-Q and STAD-Q
Software sets up DST-Q elements with predefined UserHandle values and pointing to
empty buffers. As shown in
element is updated with a handle value of the last DST-Q element used by the packet and
the corresponding packet length. Software thus maintains the number of DST-Q elements
used (that is, buffers used and the appropriate buffer fragment pointers) for a particular
status completion.
AXI Interconnect
The AXI Interconnect is used to connect the various IPs together in a memory-mapped
system. The interconnect is responsible for:
• Converting AXI3 transactions from the AXI-PCIe bridge into AXI4 transactions for
various slaves
• Decoding address to target the appropriate slave
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Figure 5-4, packet-0 spans across three SRC-Q elements. The third element
Figure 5-4: SRC-Q and STAS-Q
Figure 5-4, packet-0 spans two DST-Q elements. One STAD-Q
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