Xilinx KCU105 User Manual page 46

See LogiCORE IP AXI Interconnect Product Guide (PG059)
Two interconnects are connected in a hierarchical fashion to segregate the bursty DMA
transactions and AXI4-Lite transactions, which helps improve the timing closure of the
design. There are two slaves connected to the AXI4-Lite interconnect in the base design.
The AXI interconnect directs the read/write requests to the appropriate slaves based on the
address hit shown in
Table 5-2: AXI4-Lite Slaves Address Decoding
AXI4-Lite Slave
GenCheck
User space registers
AXI Performance Monitor
Hardware SGL Interfacing
The hardware SGL interface
to DMA channels. This is useful in a FIFO mode of operation. The logic designed handles
both S2C and C2S traffic scenarios.
X-Ref Target - Figure 5-5
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Table 5-2.
0x44A00000 - 0x44A0FFF
0x44A01000 - 0x44A01FFF
0x44A10000 - 0x44A1FFFF
(Figure 5-5) allows the design to provide SGL elements directly
Figure 5-5: Hardware SGL Interfacing
www.xilinx.com
[Ref 8] for more details.
Address Range
Send Feedback
Size
4K
4K
64K
46