Xilinx KCU105 User Manual page 70

Check the status of the design using the KCU105 board LEDs. The design provides status
with the GPIO LEDs located on the upper right portion of the KCU105 board. When the PC
is powered on and the TRD has successfully configured, the LED status from left to right
indicates these conditions (see
• LED position 6: ON if reset for both the PHYs are done
• LED position 5: ON if the PHY1 Link is up
• LED position 4: ON if the PHY0 Link is up
• LED position 3: ON if the link speed is Gen2, else flashing (Link Speed Error)
• LED position 2: ON if the lane width is x8, else flashing (Lane Width Error)
• LED position 1: Heartbeat LED, flashes if PCIe user clock is present
• LED position 0: ON if the PCIe link is UP
The LED position numbering used here matches LED positions on the board.
Note:
X-Ref Target - Figure 5-15
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Figure 5-15):
Figure 5-15: GPIO LED Indicators for Ethernet
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