Software - Xilinx KCU105 User Manual

6. DMA updates STAS-Q after transfer completion.
7. Hardware SGL Prepare block converts the AXI MM data from DMA to AXI Streaming data
to Generator/Checker block.
C2S Traffic Flow
1. Host maintains DST-Q, STAD-Q.
2. Hardware SGL block provides SRC-Q through hardware SGL interface.
3. DMA fetches DST-Q.
4. DMA fetches buffer pointed to by SRC-Q.
5. Due to use of a hardware SGL interface, DMA does not fetch SRC-Q and there is no
STAS-Q involved.
6. Hardware SGL Prepare block converts the AXI Streaming data from Generator/Checker
to AXI MM data to Northwest Logic DMA.
7. DMA writes buffer to address pointed to by DST-Q and updates STAD-Q after
completion of transfer.
The address regions to be used on card memory can be pre-defined or advertised by the user
Note:
logic registers. This design uses predefined regions.
The section on
described above can be extended to include a user application block.

Software

Expresso DMA Driver Design
The section describes the design of the PCIe Expresso DMA (XDMA) driver with the
objective of enabling use of the XDMA driver in the software stack.
Prerequisites
An awareness of the Expresso DMA hardware design and a basic understanding of the PCIe
protocol, software engineering fundamentals, and Windows and Linux OS internals are
required.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Setup Procedure for 2x10G Ethernet Design, page 69
www.xilinx.com
explains how the steps
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