Chapter 4: Implementing And Simulating The Design; Implementing The Base Design - Xilinx KCU105 User Manual

Implementing and Simulating the Design
This chapter describes how to implement and simulate the targeted reference design. The
time required to do so can vary from system to system depending on the control computer
configuration.
In Windows, if the project directory path length is more than 260 characters, design
Note:
implementation or simulation using Vivado Design Suite might fail due to a Windows OS limitation.
KCU105 Evaluation Kit Master Answer Record (AR 63175)
Refer to the

Implementing the Base Design

1. If not already done so, copy the reference design ZIP file to the desired directory on the
control PC and unzip the ZIP file. (The TRD files were extracted to your
<working_dir> in
2. Open a terminal window on a Linux system with the Vivado environment set up, or open
a Vivado tools Tcl shell on a Windows system.
3. Navigate to the kcu105_axis_dataplane/hardware/vivado/scripts folder.
4. To run the implementation flow in GUI mode, enter:
$ vivado -source trd03_base.tcl
This opens the Vivado Integrated Design Environment (IDE), loads the block diagram,
and adds the required top file and Xilinx design constraints (XDC) file to the project (see
Figure 4-1).
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Download the Targeted Reference Design Files, page
www.xilinx.com
Chapter 4
for more details.
10).
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