Xilinx KCU105 User Manual page 94

Table C-12: MAC_1_ID_LOW Register (0x44A0_1410)
Bit Position Mode
31:0 R/W
Table C-13: MAC_1_ID_HIGH Register (0x44A0_1414)
Bit Position Mode
31:16 Read only
15:0 R/W
Table C-14: PHY_0_STATUS Register (0x44A0_1418)
Bit Position Mode
31:6 Read only
15:8 Read only
7:0 Read only
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Default Value
Ethernet MAC 1 address lower 32 bits.
0xDDCCBBAA
Default Value
Reserved
0x0000
Ethernet MAC 1 address upper 16 bits.
0xFFEE
Default Value
Reserved
0x0000
PHY 0 Status. LSB bit represents PHY link up status.
0x00
PHY 1 Status. LSB bit represents PHY link up status.
0x00
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Appendix C: Register Space
Description
Description
Description
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