Xilinx KCU105 User Manual page 49

X-Ref Target - Figure 5-7
Hardware SGL Prepare Block
The hardware SGL Prepare block implements the data memory for temporary data
buffering, SGL Prepare logic, and a protocol conversion logic for data conversion from AXI
memory-mapped (MM) to AXI-Stream and vice versa.
PCIe Streaming Data Plane TRD
UG920 (v2017.1) June 01, 2017
Chapter 5: Targeted Reference Design Details and Modifications
Figure 5-7: SGL Allocation FSM
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