Timer 2 Interrupt Control Register; Table 15-32. Int_Ctrl Register; Table 15-33. Int_Ctrl Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

15.2.2.15 Timer 2 Interrupt Control Register

BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR

Table 15-32. INT_CTRL Register

31 30 29 28 27
0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0
R R R R R

Table 15-33. INT_CTRL Register Definitions

BITS FIELD NAME
31:5 /// Reserved Read as zero.
Timer 2 Interrupt Enable During Capture Operation
4 CAP1_EN
0 = No interrupt request occurs for Capture 1.
1 = Interrupt request occurs for Capture 1.
Timer 2 Interrupt Enable During Capture Operation
3 CAP0_EN
0 = No interrupt request occurs for Capture 0.
1 = Interrupt request occurs for Capture 0.
Timer 2 Interrupt Enable Upon Compare 1
2 CMP1_EN
0 = No interrupt request occurs for Compare 1.
1 = Interrupt request occurs for Compare 1.
Timer 2 Interrupt Enable Upon Compare
1 CMP0_EN
0 = No interrupt request occurs for Compare 0.
1 = Interrupt request occurs for Compare 0.
Timer 2 Interrupt Overflow Enable
0 OVF_EN
0 = No interrupt request occurs when Counter 1 overflows.
1 = Interrupt request occurs when Counter 1 overflows.
26 25 24 23
///
0 0 0 0 0
R R R R
10 9 8 7
///
0 0 0 0 0
R R R R
0xFFFC4000 + 0x54
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
0 0 0 0 0
R R RW RW RW
Timers
17 16
0 0
R R
1 0
0 0
RW RW
15-27