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Static Memory Controller
There are a number of variations to the write process:
• The nCSx signal will be de-asserted one cycle earlier if the next cycle is to be a write
(see Figure 7-2).
• If the external bus is not as wide as the data in the transaction, the SMC buffers the data
and issues further external write cycles, modifying the address as needed to complete
the transaction.
• If the given memory bank is write-protected, the SMC does not try to perform the write;
rather, it returns an error status on the AHB to indicate to the AHB bus master that initi-
ated the transaction that the transaction failed. ROM banks are normally write-protected;
however, any type of memory bank can be write-protected.
7.2.2 SMC Read Process
The SMC read process, shown in Figure 7-3, is similar to the SMC write process, except
that no data is presented. The nCSx signal is asserted on the same cycle and the address
is placed on A[23:0]. Each SMC bank has a programmable number of wait states.
The SMC also supports an nWAIT input that an external device can use to vary the wait
time. If there are N (1 < N < 32) wait states, the SMC holds this state for either N clock
cycles or until nWAIT is sampled as being inactive — whichever happens last. The SMC
captures the data on the following edge of the system clock following the assertion of
nCSx. The nCSx signal and the address are removed one cycle later. If the external mem-
ory interface is not as wide as the AHB transfer request, the SMC issues successive exter-
nal read bus cycles and buffers the data before it is presented to the AHB. The AHB
remains unavailable for any other purpose until the read request has been completed.
7.2.3 SMC Burst Mode Read Process
The SMC supports a Burst Mode, shown in Figure 7-4. This mode supports sequential
access burst reads of up to four consecutive locations in 8- or 16-bit memories. This fea-
ture supports Burst Mode ROM devices and increases the bandwidth by using a reduced
(configurable) access time for three sequential reads following a quad-location boundary
read. The number of wait states for the initial read, and for subsequent reads, are sepa-
rately programmable.
Quad-location boundaries occur when HADDR[1:0] = 00 for byte-wide memories or when
HADDR[1] = 0 for halfword memories (refer to Table 7-2).
Accesses must be made on appropriate word boundaries. A bus error occurs:
• If a 16-bit access is made on an odd address, or
• If a 32-bit access is made on a 2-word boundary (A[1:0] = 10b).
7-4
LH75400/01/10/11 (Preliminary) User's Guide
6/17/03
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