Real-Time Clock
17.3.2 RTC Register Definitions
17.3.2.1 Data Register 0
DR0 is the Lower 16-bit Read Data Register. Reads from this register return the current
value of the lower 16 bits of the counter. When this register is read, the DR1 Register is
updated with the current value of the upper 16 bits of the counter.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
NOTE: The reset value of this register's bits is indeterminate.
BIT
31:16
15:0
17-4
31
30
29
28
27
—
—
—
—
—
R
R
R
R
R
15
14
13
12
11
—
—
—
—
—
R
R
R
R
R
Table 17-3. DR0 Register Definitions
NAME
///
Reserved
RTCDR0 RTC Data Register 0 Specifies the current lower 16-bit counter value.
LH75400/01/10/11 (Preliminary) User's Guide
Table 17-2. DR0 Register
26
25
24
23
///
—
—
—
—
R
R
R
R
10
9
8
7
RTCDR0
—
—
—
—
R
R
R
R
0xFFFE0000 + 0x00
DESCRIPTION
6/17/03
22
21
20
19
18
—
—
—
—
—
R
R
R
R
R
6
5
4
3
2
—
—
—
—
—
R
R
R
R
R
17
16
—
—
R
R
1
0
—
—
R
R