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Static Memory Controller
BITS
31:30
29:28
27
26
25
24
23:16
15:11
10
9:5
4
3:0
7-14
Table 7-11. BCR0 Register Definitions
NAME
Reserved Do not write. Must be set to 00. Unpredictable behavior if set to
///
any other value. Read as zero.
Memory Width
00 = 8-bit
MW
01 = 16-bit
10 = Reserved
11 = Reserved
Burst Mode
BM
0 = Non-burst devices (Default)
1 = Burst ROM
Write Protect
WP
0 = SRAM, not write protected (Default)
1 = ROM, burst ROM and write-protected SRAM
Write Protect Error Status Flag
0 = No error (Default)
WPERR
1 = Write-protect error
Writing a 1 to this bit clears the write-protect error-status flag.
Bus Transfer Error Status Flag
0 = No error (Default)
BUSERR
1 = Bus-transfer error
Writing a 1 to this bit clears the bus-transfer error-status flag.
///
Reserved Do not write. Do not modify. Unpredictable behavior when read.
Wait State2
For SRAM: WST2 is the write access time burst access time for burst ROM.
The wait state time is (WST2 + 1) × tHCLK.
WST2
For Burst ROM: WST2 is the burst access time. This wait state time is
(WST2) × tHCLK. WaitState2 does not apply to on-burst ROM devices.
(Default = 11111)
Read Byte Lane Enable: 2
0 = All byte lane strobes nBLE[1:0] held HIGH during reads from off-chip
memory (default at System Reset). During writes, the appropriate
RBLE
nBLE[1:0] pins are held LOW and the nWE pin is held HIGH.
1 = All byte lane strobes nBLE[1:0] held LOW during reads from off-chip mem-
ory. During writes, nWE and the appropriate nBLE[1:0] pins are held LOW.
Wait State1
For SRAM and ROM: WST1 is the read access time burst access time for
WST1
burst ROM.
For Burst ROM: WST1 is the initial access time. This wait state time is (WST2)
× tHCLK. The wait state time is (WST1 + 1) × tHCLK. (Default = 11111)
///
Reserved Do not write. Do not modify. Unpredictable when read.
Idle Cycle Memory Data Bus Turnaround Time The turnaround time is
IDCY
(IDCY + 1) × tHCLK. (Default = 1111).
LH75400/01/10/11 (Preliminary) User's Guide
DESCRIPTION
6/17/03
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