Table 12-7. Dma Burst Size; Table 12-6. Dma Data Width - Sharp Blue Treak LH75400 User Manual

Direct Memory Access Controller
BIT
4:3
2
1
0
12-10
Table 12-5. CTRL Register Definitions (Cont'd)
NAME
Source-to-DMA data width See Table 12-6. For memory-to-peripheral operations,
SoSize
if bits [6:5] = '00', bits [4:3] must = '00'. If bits [6:5] = '01', bits [4:3] must = '01'.
Current Destination Register Increment Enables the Current Destination Register
increment after each DMA-to-destination data transfer.
DeInc
0 = Current Destination Register remains unchanged.
1 = Current Destination Register is incremented.
Current Source Register Increment Enables the Current Source Register incre-
ment after each source-to-DMA data transfer.
0 = Current Source Register remains unchanged, holding the same value during the
SoInc
entire DMA transfer.
1 = Current Source Register increments as data transfers from a source to the DMA.
The value increments by the HSIZE value at the end of the address phase of the
AHB transfer.
DMA Controller Enable/Disable
Source Base, Destination Base, and Maximum Count Registers must be set before the
DMA is enabled. The state machine clears this bit when a data transfer finishes. If the
Enable
software resets this bit during a transfer, that stream interface is reset.
0 = DMA data transfer is disabled.
1 = DMA data transfer is enabled.

Table 12-6. DMA Data Width

SoSize/DeSize
NOTE: If you use a SoSize/DeSize of '01', set the
SoBurst value to '01'.

Table 12-7. DMA Burst Size

SoBurst
LH75400/01/10/11 (Preliminary) User's Guide
FUNCTION
Enables or disables the DMA Controller. The
AHB DATA WIDTH
00 1 byte
01 1 half-word (2 bytes)
10 1 word (4 bytes)
11 Reserved
AHB BURST TYPE
00 Single
01 4 incrementing
10 8 incrementing
11 16 incrementing
7/15/03