Masked Interrupt Status Register; Table 19-27. Mis Register; Table 19-28. Mis Register Definitions - Sharp Blue Treak LH75400 User Manual

UART0 and UART1

19.3.1.14 Masked Interrupt Status Register

MIS is the Masked Interrupt Status Register. On a read, this register returns the current
masked status value of the corresponding interrupt. A write has no effect.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:11
10
9
8
7
6
5
4
3:0
19-22
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 19-28. MIS Register Definitions

NAME
///
OVERRUN ERROR
MASKED INTERRUPT
STATUS
BREAK ERROR MASKED
INTERRUPT STATUS
PARITY ERROR MASKED
INTERRUPT STATUS
FRAMING ERROR
MASKED INTERRUPT
STATUS
RECEIVE TIMEOUT
MASKED INTERRUPT
STATUS
TRANSMIT MASKED
INTERRUPT STATUS
RECEIVE MASKED
INTERRUPT STATUS
///
LH75400/01/10/11 (Preliminary) User's Guide

Table 19-27. MIS Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
0 0 0 0
R R R R
UART0: 0xFFFC0000 + 0x040
UART1: 0xFFFC1000 + 0x040
Reserved Do not modify.
Overrun Error Masked Interrupt Status Specifies the
masked interrupt state (after masking) of the
UARTOEINTR interrupt.
Break Error Masked Interrupt Status Specifies the
masked interrupt state (after masking) of the
UARTBEINTR interrupt.
Parity Error Masked Interrupt Status Specifies the
masked interrupt state (after masking) of the
UARTPEINTR interrupt.
Framing Error Masked Interrupt Status Specifies the
masked interrupt state (after masking) of the
UARTFEINTR interrupt.
Receive Timeout Masked Interrupt Status Specifies
the masked interrupt state (after masking) of the
UARTRTINTR interrupt.
Transmit Masked Interrupt Status Specifies the
masked interrupt state (after masking) of the
UARTTXINTR interrupt.
Receive Masked Interrupt Status Specifies the
masked interrupt state (after masking) of the
UARTRXINTR interrupt.
Reserved Do not modify.
7/15/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
0 0 0 0 0
R R R R R
DESCRIPTION
17 16
0 0
R R
1 0
///
0 0
R R