Bus Timing Register 0; Table 22-12. Btr0 Register; Table 22-13. Btr0 Register Definitions - Sharp Blue Treak LH75400 User Manual

Controller Area Network

22.3.2.6 Bus Timing Register 0

BTR0 is one of two CAN Timing Registers (BTR1 is the other). Together, these two regis-
ters define the structure of the bit period.
The BTR0 Register defines the values of the Synchronization Jump Width (SJW) and the
Bit Rate Prescaler (BRP). This register can only be written to in Reset Mode. In Operating
Mode, it is Read Only.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:6
5:0
22-14

Table 22-12. BTR0 Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 22-13. BTR0 Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Synchronization Jump Width Defines the maximum number of clock
cycles by which a bit period can be shortened or lengthened in attempt-
SJW ing to re-synchronize on the relevant signal edge (recessive to domi-
nant) of the current transmission. The number of clock cycles range from
0 to 3.
Bit Rate Prescaler Defines the period (time quantum) of the CAN
clock tSCL as a multiple of the system clock period. The time quantum
of the CAN clock is given by:
BRP4 - BRP0
tSCL =2 × tCLK × ((32 × BRP.5) + (16 × BRP.4) + (8 × BRP.3) +
(4 × BRP.2) + (2 × BRP.1) + BRP.0 + 1)
where tCLK = time period of the system clock frequency = 1/ƒSYSTEM CLK
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
SJW SJW BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
0 0 0 0 0
R R R R R
0xFFFC5000 + 0x18
DESCRIPTION
6/17/03
21 20 19 18 17
0 0 0 0 0
R R R R R
5 4 3 2 1
0 0 0 0 0
R R R R R
16
0
R
0
0
R