UART2
20.3.2.15 FIFO Level Register
Register Bank: 1
FLR is the FIFO Level Register. The FLR Register holds the current Receive and Transmit
FIFO occupancy levels.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:7
6:4
3
2:0
20-26
31
30
29
28
27
0
0
0
0
R
R
R
R
15
14
13
12
11
0
0
0
0
R
R
R
R
Table 20-40. FLR Register Definitions
NAME
///
Reserved Do not modify. Read as zero.
Receive FIFO Level of Occupancy Indicates the number of char-
RFL2, RFL1, RFL0
acters in the Receive FIFO. The valid range is from zero (000) to
four (100).
///
Reserved Read as zero.
Transmit FIFO Level of Occupancy Indicates the number of
TFL2, TFL1, TFL0
characters in the Transmit FIFO. The valid range is from zero (000)
to four (100).
LH75400/01/10/11 (Preliminary) User's Guide
Table 20-39. FLR Register
26
25
24
23
///
0
0
0
0
0
R
R
R
R
R
10
9
8
7
///
0
0
0
0
0
R
R
R
R
R
0xFFFC2000 + 0x10
DESCRIPTION
6/17/03
22
21
20
19
18
0
0
0
0
R
R
R
R
R
6
5
4
3
RFL2 RFL1 RFL0
///
TFL2 TFL1 TFL0
0
0
0
0
R
R
R
R
R
17
16
0
0
0
R
R
2
1
0
0
0
0
R
R