Status Register; Table 22-6. Sr Register - Sharp Blue Treak LH75400 User Manual

Controller Area Network

22.3.2.3 Status Register

SR is the Status Register. The SR Register reflects the status of the CAN Controller. It
appears to the CPU as Read Only memory.
If bits [5] and [4] are both 0, the CAN bus is idle. If both bits are 1, the Controller is waiting
to become idle again. After a System Reset, Idle state is entered once the Bus Free
sequence (11 consecutive recessive bits) is detected. After a Bus Off event, 128 Bus Free
sequences must be received before Idle state is entered.
When using this register:
• If both the Receive Status and the Transmit Status bits are '0', the CAN bus is idle. If
both bits are '1', the CAN Controller is waiting to become idle again. After a System
Reset, Idle state is entered once the Bus Free sequence (11 consecutive recessive bits)
is detected. After a Bus Off event, 128 Bus Free sequences must be received before Idle
state is entered.
• For bit [1], the overrun condition is only indicated if the entire message was received. No
overrun condition is shown if the message did not complete (e.g., due to an error).
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
22-10
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R
LH75400/01/10/11 (Preliminary) User's Guide

Table 22-6. SR Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
BS
0 0 0 0
R R R R
0xFFFC5000 + 0x08
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
ES TS RS TCS TBS
0 1 1 1 1
R R R R R
17 16
0 0
R R
1 0
DOS RBS
0 0
R R