Uart2 Programmer's Model; Uart2 Register Summary; Table 20-1. Register Bank 0 (Default On Reset) - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

20.3 UART2 Programmer's Model

The base address for UART2 is:
UART2 Base Address: 0xFFFC2000

20.3.1 UART2 Register Summary

The Configuration, Status, and Control Registers are contained in one of four banks.
Selection of banks 0 to 3 is accomplished by writing to the GIR Register bits 6 and 5. The
GIR Register is accessible at the same address for all register banks. See Table 20-1 for
more details.
The registers are considered static, except for changes in status due to incoming and out-
going characters, changes due to interrupt generation, and changes in status due to reg-
ister access via the programming interface.
20.3.1.1 Register Bank 0
DLAB (Divisor Latch Access Bit) is a bit in the Line Configure Register (LCR). See
Section 20.3.2.7.
NAME
TXD
RXD
BAL
BAH
GER
GIR
LCR
MCTRL
LSR
///
ACTRL0

Table 20-1. Register Bank 0 (Default On Reset)

ADDRESS
DLAB TYPE
OFFSET
0x00 0 W
0x00 0 R
0x00 1 RW
0x04 1 RW
0x04 0 RW
0x08 RW
0x0C RW
0x10 RW
0x14 RW
0x18
0x1C RW
RESET
VALUE
— Transmit Buffered Data Register
0x00 Receive Buffered Data Register
BRGA Divisor Least Significant Byte Register.
0x02 The DLAB bit in the LCR Register must be set
to access this register.
BRGA Divisor Most Significant Byte Register.
0x00 The DLAB bit in the LCR Register must be set
to access this register.
0x00 General Enable Register
0x01 General Interrupt Register/Bank Register
0x00 Line Control Register
0x00 Loopback Control Register
0x60 Line Status Register
Reserved
0x00 Address/Control Character Register 0
6/17/03
UART2
DESCRIPTION
20-7