Uart2 Register Definitions; Transmit Buffered Data Register; Table 20-5. Txd Register; Table 20-6. Txd Register Definitions - Sharp Blue Treak LH75400 User Manual

UART2

20.3.2 UART2 Register Definitions

20.3.2.1 Transmit Buffered Data Register

Register Banks: 0 and 1
TXD is the Transmit Buffered Data Register. The active bits used in this register are Write
Only. The TXD Register holds the next data byte to be pushed into the Transmit FIFO.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
NOTE: The reset value of this register's bits is indeterminate.
BITS
31:8
7:0
20-10
31 30 29 28 27
— — — — —
R R R R R
15 14 13 12 11
///
— — — — —
R R R R R

Table 20-6. TXD Register Definitions

NAME
/// Reserved Do not modify. Read as zero.
Transmitted Data Bit [7] holds the most-significant bit. Bit [0] holds the
D7:D0
least-significant bit.
LH75400/01/10/11 (Preliminary) User's Guide

Table 20-5. TXD Register

26 25 24 23
///
— — — —
R R R R
10 9 8 7
D7
— — — —
R R R W
0xFFFC2000 + 0x00
DESCRIPTION
6/17/03
22 21 20 19 18
— — — — —
R R R R R
6 5 4 3 2
D6 D5 D4 D3 D2
— — — — —
W W W W W
17 16
— —
R R
1 0
D1 D0
— —
W W