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LH75400/01/10/11 (Preliminary) User's Guide
7.2.6 SMC Memory Connection Diagram
Figure 7-5 shows connections for a typical memory system with different data width
memory devices.
A[21:1]
A[23:1]
nCS0
A[16:1]
nCS1
nWE
A[17:1]
A[17:1]
nCS2
nOE
nBLE1
nBLE0
Figure 7-5. Typical Memory Connection Diagram
6/17/03
D[15:0]
A[20:0]
Q[31:0]
nCE
nOE
2M × 16 BURST MASK ROM
D[15:0]
A[15:0] IO[15:0]
nCE
nOE
nWE
nUB
nLB
64K × 16 SRAM
D[15:8]
A[16:0]
IO[7:0]
nCE
nOE
nWE
128K × 8 SRAM
D[7:0]
A[16:0]
IO[7:0]
nCE
nOE
nWE
128K × 8 SRAM
Static Memory Controller
D[15:0]
LH754xx-8
7-11
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