Transmit Error Counter Register - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary
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Controller Area Network

22.3.2.12 Transmit Error Counter Register

TXERR is the Transmit Error Counter Register. The TXERR Register records the current
value of the Transmit Error Counter. This register works with the Receive Error Counter
(described in Section 22.3.2.11) to create a metric for communication quality based on his-
toric performance.
After a System Reset, the Transmit Error Counter is automatically set to '0'. However, if
the CAN Controller enters Reset Mode as a result of a Bus Off event, the register is initial-
ized instead to 127 to count the minimum protocol-defined time before the CAN Controller
can take part in further transmission on the CAN bus (128 occurrences of the Bus Free
sequence of 11 consecutive recessive bits). Reading the Transmit Error Counter during
this time indicates the status of the Bus Off recovery.
The TXERR Register can only be written to in Reset Mode. In Operating Mode, this regis-
ter appears to the CPU as Read Only memory.
While in Bus Off state, writing a value in the range from 0 to 254 to the TXERR Register
clears the Bus Off flag. The CAN Controller then waits one Bus Free sequence after the
Reset Mode clears.
Writing 255 to the TXERR Register initiates a CPU-driven bus-off event. Note that a CPU-
forced content change of the transmit error counter is only possible if Reset Mode was
entered previously. An error or bus status change (see Section 22.3.2.3), an error warning,
or an error passive interrupt forced by the new register content will not occur until the Reset
Mode is canceled again. After leaving Reset Mode, the new transmit counter content is
interpreted and the Bus Off event is performed as if it was forced by a bus error event.
This means that:
• Reset Mode is entered again.
• The transmit error counter is initialized to 127.
• The receive counter is cleared.
• The relevant status and interrupt register bits are set.
Clearing of Reset Mode now performs the protocol-defined Bus Off recovery sequence
(waiting for 128 occurrences of the Bus Free signal).
If Reset Mode is entered again before the Bus Off recovery completes (TXERR > 0), Bus
Off stays active, with TXERR frozen until the CAN Controller returns to Operating Mode.
22-22
LH75400/01/10/11 (Preliminary) User's Guide
6/17/03

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