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Vectored Interrupt Controller
11. After an FIQ or IRQ line into the CPU is asserted, the CPU takes over processing of the
interrupt by switching internally to the applicable Processor Mode (either FIQ or IRQ).
12. If the interrupt is an FIQ interrupt, CPU processing should follow normal ARM conven-
tions for processing FIQ interrupts. For more information, consult the ARM literature
at www.arm.com.
13. If the interrupt is an IRQ interrupt, low-latency processing is invoked by the program-
ming the instruction:
at location 0x18 (the CPU IRQ Exception Vector) in the CPU memory map.
14. If global IRQ interrupts are enabled in the CPSR of the CPU, the instruction at address
0x18 is the first instruction executed when any IRQ exception is invoked. Executing
this instruction immediately loads the VectAddr Register value into the program
counter as the address of the next instruction to be executed. Since the VIC loads
VectAddr with the entry address for the specific interrupt handler for the associated
signal, ISR processing begins with the next instruction, without needing to determine
the interrupt source. Similarly, if the interrupt is default-vectored, the VIC loads the
Default Vector Address into the VectAddr Register. For default-vectored interrupts,
the ISR determines the source of the interrupt and handles it appropriately.
15. FIQ and IRQ interrupts are globally disabled by the CPU when an FIQ is asserted.
IRQ interrupts are globally disabled by the CPU when an IRQ is asserted. The timing
and circumstances of re-enabling global interrupts and implementing interrupt nesting
are implementation specific, and special precautions to save and restore context must
be taken. Global interrupts should be re-enabled upon invoking the conventional
means of returning from a single (non-nested) interrupt.
16. Before returning from an interrupt, the interrupt must be cleared at the source and a
WRITE operation to the VIC VectAddr Register must be executed — in this order. This
sequence clears the interrupt, and notifies the interrupt and priority logic that the next
interrupt can be processed by the hardware. The next interrupt might be pending, or
it might be asynchronously asserted at a later time; however, the sequence of inter-
rupt processing by the VIC is the same for each.
A pending interrupt is serviced immediately upon the return from handling the current inter-
rupt. This occurs because the VIC hardware immediately reasserts the IRQ line to the CPU
when the VIC VectAddr Register is written. However, when interrupt nesting is not permit-
ted, the interrupt is not acted upon until the global IRQ interrupts are re-enabled.
10-6
0x18LDR PC, [PC,#-0xFF0]
LH75400/01/10/11 (Preliminary) User's Guide
6/17/03
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