Dma Programmer's Model; Dma Controller Register Summary; Table 12-2. Dma Register Summary; Table 12-3. Data Stream Register Summary - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

12.3 DMA Programmer's Model

The base address for the DMA Controller is:
DMA Base Address: 0xFFFE1000
The DMA Registers are accessed via the APB; the register data path is 16 bits wide. The
register offsets for the DMA Controller are defined in Table 12-2.

12.3.1 DMA Controller Register Summary

The registers from 0x000 to 0x0EC are the Stream Configuration Registers, of which there
is a set of registers for each data stream. The registers for each stream are shown in
Table 12-3.

Table 12-2. DMA Register Summary

NAME ADRESS OFFSET TYPE
Stream0 0x000
Stream1 0x040
Stream2 0x080
Stream3 0x0C0
Mask 0x0F0
Clr 0x0F4
Status 0x0F8

Table 12-3. Data Stream Register Summary

ADDRESS
NAME
OFFSET
SourceLo 0x000
SourceHi 0x004
DestLo 0x008
DestHi 0x00C
Max 0x010
Ctrl 0x014
SoCurrHi 0x018
SoCurrLo 0x01C
DeCurrHi 0x020
DeCurrLo 0x024
TCnt 0x028
/// 0x2C - 0x3C
Direct Memory Access Controller
DESCRIPTION
RW Data Stream0 Register Base
R W Data Stream1 Register Base
RW Data Stream2 Register Base
RW Data Stream3 Register Base
RW DMA Interrupt Mask Register
W DMA Interrupt Clear
R DMA Status Register
TYPE DESCRIPTION
RW Source base address, lower 16 bits
RW Source base address, higher 16 bits
RW Destination base address, lower 16 bits
RW Destination base address, higher 16 bits
RW Maximum Count Register
RW Control Register
R Current source address, higher 16 bits
R Current source address, lower 16 bits
R Current destination address, lower 16 bits
R Current destination address, higher 16 bits
R Terminal counter
— Reserved
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