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UART2
The start bit works with the system clock to synchronize the receiver with the source driving
the receiver. The start-bit verification can be performed through a majority-voting system
or an absolute voting system.
• With absolute voting, all samples must agree. Otherwise, a false start bit is determined
and the receiver returns to the Start Bit Search Mode.
• With majority voting, start-bit verification works according to the Sampling Mode in effect:
– For 3/16 Sampling Mode, the UART recognizes a start bit if the input is 0 for at least
two of the three samples.
– For 7/16 Sampling Mode, the UART recognizes a start bit if the input is 0 for at least
four of the seven samples.
After recognizing the start bit, the receiver repeats one of the following sequences until all
data bits, any parity bit, and all stop bits are detected:
• 3/16 Sampling Mode
1. Wait 14/16ths of a bit period, then sample the input.
2. Wait 1/16th of a bit period, then sample the input.
3. Wait 1/16th of a bit period, then sample the input.
4. Choose the majority value of the three samples as its input value for that bit period.
• 7/16 Sampling Mode
1. Wait 10/16ths of a bit period, then sample the input.
2. Wait 1/16th of a bit period, then sample the input.
3. Wait 1/16th of a bit period, then sample the input.
4. Wait 1/16th of a bit period, then sample the input.
5. Wait 1/16th of a bit period, then sample the input.
6. Wait 1/16th of a bit period, then sample the input.
7. Wait 1/16th of a bit period, then sample the input.
8. Choose the majority value of the seven samples as its input value for that bit period.
After recognizing the final stop bit, the UART stores the received data frames and associ-
ated status bits in the receiver FIFO.
20-4
LH75400/01/10/11 (Preliminary) User's Guide
6/17/03
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