Interrupt Mask Set/Clear Register; Table 19-23. Imsc Register; Table 19-24. Imsc Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

19.3.1.12 Interrupt Mask Set/Clear Register

IMSC is the Interrupt Mask Set/Clear Register. The active bits used in this register are
Read/Write.
On a read, this register returns the current value of the mask on the relevant interrupt. On
a write of '1' to the particular bit, it enables the interrupt. A write of '0' masks the corre-
sponding interrupt. All the bits are cleared to 0 following a System Reset.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:11
10
9
8
7

Table 19-23. IMSC Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 19-24. IMSC Register Definitions

NAME
/// Reserved Do not modify.
Overrun Error Interrupt Mask Write values:
OVERRUN ERROR 0 = Clears the mask.
INTERRUPT MASK 1 = Sets the mask of the OEIM interrupt.
When Read, returns the current mask for the OEIM interrupt.
Break Error Interrupt Mask Write values:
BREAK ERROR 0 = Clears the mask.
INTERRUPT MASK 1 = Sets the mask of the BEIM interrupt.
When Read, returns the current mask for the BEIM interrupt.
Parity Error Interrupt Mask Write values:
PARITY ERROR 0 = Clears the mask.
INTERRUPT MASK 1 = Sets the mask of the PEIM interrupt.
When Read, returns the current mask for the PEIM interrupt.
Framing Error Interrupt Mask Write values:
FRAMING ERROR 0 = Clears the mask.
INTERRUPT MASK 1 = Sets the mask of the FEIM interrupt.
When Read, returns the current mask for the FEIM interrupt.
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
0 0 0 0 0
RW RW RW RW RW
UART0: 0xFFFC0000 + 0x038
UART1: 0xFFFC1000 + 0x038
DESCRIPTION
7/15/03
UART0 and UART1
21 20 19 18 17
0 0 0 0 0
R R R R R
5 4 3 2 1
///
0 0 0 0 0
RW RW R R R
16
0
R
0
0
R
19-19