Raw Interrupt Status Register; Table 19-25. Ris Register; Table 19-26. Ris Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

19.3.1.13 Raw Interrupt Status Register

RIS is the Raw Interrupt Status Register. On a read, this register returns the current raw
status value of the corresponding interrupt. A write has no effect.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:11
10
9
8
7
6
5
4
3:0

Table 19-25. RIS Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 19-26. RIS Register Definitions

NAME
///
OVERRUN ERROR
INTERRUPT STATUS
BREAK INTERRUPT
STATUS
PARITY ERROR
INTERRUPT STATUS
FRAMING ERROR
INTERRUPT STATUS
RECEIVE TIMEOUT
INTERRUPT STATUS
TRANSMIT INTERRUPT
STATUS
RECEIVE INTERRUPT
STATUS
///
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
0 0 0 0 0
R R R R R
UART0: 0xFFFC0000 + 0x03C
UART1: 0xFFFC1000 + 0x03C
DESCRIPTION
Reserved Do not modify.
Raw Interrupt State Specifies the raw interrupt state (pri-
or to masking) of the UARTOEINTR interrupt.
Break Interrupt Status Specifies the raw interrupt state
(prior to masking) of the UARTBEINTR interrupt.
Parity Error Interrupt Status Specifies the raw interrupt
state (prior to masking) of the UARTPEINTR interrupt.
Framing Error Interrupt Status Specifies the raw inter-
rupt state (prior to masking) of the UARTFEINTR interrupt.
Receive Timeout Interrupt Status Specifies the raw
interrupt state (prior to masking) of the UARTRTINTR
interrupt.
Transmit Interrupt Status Specifies the raw interrupt
state (prior to masking) of the UARTTXINTR interrupt.
Receive Interrupt Status Specifies the raw interrupt state
(prior to masking) of the UARTRXINTR interrupt.
Reserved Do not modify.
7/15/03
UART0 and UART1
21 20 19 18 17
0 0 0 0 0
R R R R R
5 4 3 2 1
///
0 0 0 0 0
R R R R R
16
0
R
0
0
R
19-21