Receive Machine Mode Register; Table 20-61. Rmd Register; Table 20-62. Rmd Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

20.3.2.26 Receive Machine Mode Register

Register Bank: 2
RMD is the Receive Machine Mode Register. The RMD Register defines the receiver oper-
ating mode. For information about manually locking the FIFO, see Section 20.3.2.16.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:8
µCM0,
7:6
5
4
3
2:0
31 30 29 28
0 0 0 0
R R R R
15 14 13 12
///
0 0 0 0
R R R R

Table 20-62. RMD Register Definitions

/// Reserved Do not modify. Read as zero.
LAN/Control Character Recognition Mode In Normal Mode, these bits define the Control
Character Recognition Mode. In µLAN Mode, these bits define modes of address recognition:
Settings for Normal Mode:
00 = No standard set Control Characters recognized
01 = ASCII Control Characters (00H through 1 FH + 7FH)
10 = Reserved
11 = EBCDIC Control Character recognized (00H – 3 FH)
Settings for µLAN Mode:
00 = Manual Mode. The receiver reports reception of any address character via CRF bit of
RST Register and writes it to the Rx FIFO.
µCM1
01 = Semi-automatic Mode. Same as Manual Mode, but the receiver opens (unlocks) the
Rx FIFO upon reception of any address characters. Subsequent received characters
are written into the FIFO. You must lock the FIFO if the address character does not
match the station's address.
10 = Automatic Mode. The receiver opens (unlocks) the Rx FIFO upon address match. Also,
the receiver locks the Rx FIFO upon recognition of address mismatch; that is, it controls
the flow of characters into the Rx FIFO, depending on the results of the address
comparison. If a match occurs, it allows characters to be sent to the FIFO; if a mismatch
occurs, it keeps the characters out of the FIFO by locking the FIFO.
11 = Reserved
Disable Digital Phase Locked Loop
DPD
1 = Disable the DPLL machine. (Using the DPLL in a very noisy media can increase the
error rate.)
Sampling Window Mode Controls the mode of data sampling.
0 = Small window, 3/16 sampling.
SWM
1 = Large window, 7/16 sampling.
Do not set bits [4] and [3] to '1' at the same time; otherwise, data may become corrupted.
Start Bit Sampling Mode Controls the mode of start-bit sampling.
0 = Majority voting for start bit: a majority of the samples determines the bit.
SSM
1 = If one of the bit samples is not 0, the start bit is not detected.
Do not set bits [3] and [4] to '1' at the same time; otherwise, data may become corrupted.
/// Reserved Read as zero.

Table 20-61. RMD Register

27 26 25 24 23
///
0 0 0 0 0
R R R R R
11 10 9 8 7
0 0 0 0 0
R R R R RW
0xFFFC2000 + 0x1C
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
DPD SSM
0 0 0 0 0
RW RW RW RW R
UART2
17 16
0 0
R R
1 0
///
0 0
R R
20-37