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General Purpose Input/Output
21.2.3.3 Port A Data Direction Register
PADDR is the Port A Data Direction Register. The active bits used in this register are
Read/Write.
Bits set in PADDR Register set the corresponding PA pin to be an output.
• Bit [7] controls pin 1 when the pin is configured as PA7. It does not control pin 1 when
the pin is configured as D15.
• Bit [6] controls pin 2 when the pin is configured as PA6. It does not control pin 2 when
the pin is configured as D14.
• Bit [5] controls pin 4 when the pin is configured as PA5. It does not control pin 4 when
the pin is configured as D13.
• Bit [4] controls pin 5 when the pin is configured as PA4. It does not control pin 5 when
the pin is configured as D12.
• Bit [3] controls pin 6 when the pin is configured as PA3. It does not control pin 6 when
the pin is configured as D11.
• Bit [2] controls pin 7 when the pin is configured as PA2. It does not control pin 7 when
the pin is configured as D10.
• Bit [1] controls pin 9 when the pin is configured as PA1. it does not control pin 9 when
the pin is configured as D9.
• Bit [0] controls pin 10 when the pin is configured as PA0. It does not control pin 10 when
the pin is configured as D8.
Clearing a bit configures the pin to be an input. A System Reset clears all bits.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
21-6
Table 21-7. PADDR Register
31
30
29
28
27
0
0
0
0
R
R
R
R
15
14
13
12
11
///
0
0
0
0
R
R
R
R
Table 21-8. PADDR Register Definitions
NAME
///
Reserved Writing to these bits has no effect. Reading returns 0.
Port A Output/Input
Port A Data Direction
Bits set = Port A output.
Bits cleared = Port A input.
LH75400/01/10/11 (Preliminary) User's Guide
26
25
24
23
///
0
0
0
0
0
R
R
R
R
R
10
9
8
7
0
0
0
0
0
R
R
R
R
RW
0xFFFDF000 + 0x08
6/17/03
22
21
20
19
0
0
0
0
R
R
R
R
6
5
4
3
Port A Data Direction
0
0
0
0
RW
RW
RW
RW
FUNCTION
18
17
16
0
0
0
R
R
R
2
1
0
0
0
0
RW
RW
RW
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