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UART0 and UART1
BIT
31:8
7
6:5
4
3
2
1
0
PARITY
ENABLE (PEN)
19-16
Table 19-17. LCTRL_H Register Definitions
NAME
///
Reserved Read as zero.
STICK PARITY
Stick Parity Select Bits [7], [2], and [1] work together to set up the
SELECT
parity. See Table 19-18.
Word Length Indicates the number of data bits transmitted or
received in a frame.
00 = 5 bits
WORD LENGTH
01 = 6 bits
10 = 7 bits
11 = 8 bits
FIFO Enable Buffers
1 = Enables transmit and receive FIFO buffers (FIFO Mode). When
ENABLE FIFOS
Frame Stop Bits
TWO STOP BITS
1 = Two stop bits are transmitted at the end of the frame. The
SELECT
EVEN PARITY
Even Parity Select Bits [7], [2], and [1] work together to set up the
SELECT
parity. See Table 19-18.
Parity Enable Bits [7], [2], and [1] work together to set up the
PARITY ENABLE
parity. See Table 19-18.
1 = A LOW level is continuously output on the UARTTXD output,
SEND BREAK
Table 19-18. Truth Table for bits [7], [2], and [1]
EVEN PARITY
SELECT (EPS)
0
X
1
1
1
0
1
0
1
1
LH75400/01/10/11 (Preliminary) User's Guide
DESCRIPTION
cleared to 0, the FIFOs are disabled (Character Mode); that is,
the FIFOs become 1-byte-deep holding registers.
receive logic always checks for received stop bits, regardless
of whether there are one or two.
after completing transmission of the current character. This bit
must be asserted for at least one complete frame transmission
time to generate a break condition. The transmit FIFO contents
remain unaffected during a break condition. For normal use,
this bit must be cleared to zero.
STICK PARITY
SELECT (SPS)
Not transmitted or checked
X
Even parity
0
Odd parity
0
1
1
0
1
7/15/03
RESULTANT PARITY BIT
(TRANSMITTED OR CHECKED)
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