Pins Pe7/Ssprm To Pe0/Uartrx2 Resistor Muxing Register; Table 11-24. Pe_Res_Mux Register Definitions - Sharp Blue Treak LH75400 User Manual

I/O Configuration

11.2.2.10 Pins PE7/SSPRM to PE0/UARTRX2 Resistor Muxing Register

PE_RES_MUX is the Pins PE7/SSPRM to PE0/UARTRX2 Resistor Muxing Register. This
register allows the pull-up/pull-down to be configured as needed. The active bits used in
this register are Read/Write.
The functions associated with bits [7:6] and [5:4] vary among the four SoCs:
• LH75400 and LH75401:
– Bits [7:6] correspond to the Pin PE3/CANTX/UARTTX0 Resistor Source.
– Bits [5:4] correspond to the Pin PE2/CANRX/UARTRX0 Resistor Source.
• LH75410 and LH75411:
– Bits [7:6] correspond to the Pin PE3/UARTTX0 Resistor Source.
– Bits [5:4] correspond to the Pin PE2/UARTRX0 Resistor Source.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:14
13:12
11:10
11-18
Table 11-23. PERES_MUX Register
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
PE7 PE6
0 1 9 0 0
RW RW RW RW RW

Table 11-24. PE_RES_MUX Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Pin PE7/SSPFRM Resistor Source
00 = Pull-down
PE7
01 = Pull-up (default)
10 = No pull-up or pull-down
11 = Pull-up
Pin PE6/SSPCLK Resistor Source
00 = Pull-down (default)
PE6
01 = Pull-up
10 = No pull-up or pull-down
11 = Pull-down
Pin PE5/SSPRX Resistor Source
00 = Pull-down
PE5
01 = Pull-up (default)
10 = No pull-up or pull-down
11 = Pull-up
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
PE5 PE4 PE3
1 9 0 0
RW RW RW RW
0xFFFE5000 + 0x24
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
PE2 PE1
1 0 1 0 1
RW RW RW RW RW
17 16
0 0
R R
1 0
PE0
0 1
RW RW