Table of Contents
Advertisement
LH75400/01/10/11 (Preliminary) User's Guide
23.3.4.1 Brownout Interrupt
The Brownout Interrupt (BrownOutINTR) is asserted when the supply voltage goes below
the trip-point voltage. This interrupt is latched and remains HIGH until the BOIC bit of the
ICR register is asserted.
This interrupt is the status of the latched value of the Brownout Interrupt stored in the Inter-
rupt Status Registers. Raw status of the Brownout is stored in the GS Register (see
Section 23.3.2.8).
The Brownout Interrupt has its own dedicated output.
NOTE: The latency between clearing the latched Brownout Interrupt and the time when that bit can be set
23.3.4.2 Pen Interrupt
The Pen Interrupt (PenIRQ) occurs when the settings on the bias switches are switched to
the Pen Interrupt Mode configuration. The Pen Interrupt is used internally to the Touch
Screen Controller as control signal for the state machine. The state machine may begin a
sequence of conversions, depending on the contents of the GC Register, when a Pen
Interrupt occurs (see Section 23.3.2.6). The PENIRQ is latched and remains HIGH until
the PENIC bit of the IC Register is asserted (see Section 23.3.2.15). It is the latched value
of the Pen Interrupt that's stored in the Interrupt Status Register. The raw status of the Pen
Interrupt is stored in the GS Register (see Section 23.3.2.8).
The Pen Interrupt has its own dedicated output.
NOTES:
1. If a measurement sequence is configured to keep the Touch Screen biased for Pen detect on every mea-
surement, PENIRQ is not generated on every sequence. If, on the other hand, the Pen detect circuit is dis-
connected, there will be an edge every time the system enters Idle state.
2. For pen-triggered interrupts, use the following procedure instead of using the WIPER's Pen Interrupt
(PENIRQ) pull-up. Before checking the Pen Down state, use bias-and-control network bit [2] to short the AN0
pin to VDDA_ADC. This discharges the capacitor formed by the Touch Screen and any capacitance added
to the AN0 pin. To generate a Pen Down Interrupt, connect AN4 to VSSA_ADC using bit [8] of the bias-and-
control network. Then connect the PENIRQ detector to AN0 using bit [12] of the bias-and-control network.
23.3.4.3 End-of-Sequence Interrupt
The End-of-Sequence Interrupt occurs after the programmed NOCs occurs. After the ADC
converts all the data for a given sequence of conversions, this interrupt goes HIGH. The
End-of-Sequence Interrupt is latched and remains HIGH until the EOSINTC bit of the IC
Register is asserted.
23.3.4.4 FIFO Watermark Interrupt
The FIFO Watermark Interrupt occurs when the number of entries in the FIFO is greater than
or equal to the programmed watermark level FIFOWMK (GC Register, bits [6:3]). This inter-
rupt clears when the FIFO level is read from and the FIFO is below the watermark level.
again is one A2DCLK cycle. Polled systems should use the unlatched Brown-Out Raw Interrupt
Status bit (bit [9]) in the GS Register (described in Section 23.3.2.8) instead of the latched interrupt
status in the ISR.
Analog-to-Digital Converter/Brownout Detector
6/25/03
23-27
Advertisement
Table of Contents
