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11.1 IOCON Theory of Operation......................................................................... 11-1
11.2 IOCON Programmer's Model ....................................................................... 11-2
12.1 DMA Controller Features.............................................................................. 12-1
12.2 DMA Theory Of Operation............................................................................ 12-2
12.3 DMA Programmer's Model ........................................................................... 12-7
13.1 CLCDC Features.......................................................................................... 13-3
13.2 CLCDC Theory of Operation ........................................................................ 13-4
13.3 CLCDC Programmer's Model..................................................................... 13-10
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11.2.1 IOCON Register Summary .................................................................... 11-2
11.2.2 IOCON Register Definitions .................................................................. 11-3
11.2.2.1 EBI Interface Muxing Register........................................................ 11-3
11.2.2.2 Pins PD6/INT6 to PD0/INT0 Muxing Register ................................ 11-5
11.2.2.3 Pins PE7/SSPRM to PD0/INT0 Muxing Register ........................... 11-6
11.2.2.4 Timer Muxing Register ................................................................... 11-8
11.2.2.5 LCD Mode Muxing Register ......................................................... 11-10
11.2.2.6 Pins PA7/D15 to PA0/D8 Resistor Muxing Register..................... 11-11
11.2.2.7 Pins PB5/nWAIT to PB0/nCS1 Resistor Muxing Register............ 11-13
11.2.2.8 Pins PC7/A23 to PC0/A16 Resistor Muxing Register................... 11-14
11.2.2.9 Pins PD6/INT6 to PD0/INT0 Resistor Muxing Register................ 11-16
11.2.2.11 Pins AN7/PJ7 to AN0/PJ0 .......................................................... 11-20
12.2.1 Interrupt, Error, and Status Registers.................................................... 12-4
12.2.2 DMA Controller Timing Diagrams.......................................................... 12-4
12.3.1 DMA Controller Register Summary ....................................................... 12-7
12.3.2 DMA Controller Register Definitions...................................................... 12-8
12.3.2.1 Source Base Registers................................................................... 12-8
12.3.2.2 Destination Base Register .............................................................. 12-8
12.3.2.3 Maximum Count Register ............................................................... 12-8
12.3.2.4 Control Register.............................................................................. 12-9
12.3.2.5 Current Source Registers ............................................................. 12-11
12.3.2.6 Current Destination Registers ...................................................... 12-11
12.3.2.7 Terminal Count Register............................................................... 12-11
12.3.2.8 Interrupt Mask Register ................................................................ 12-12
12.3.2.9 Interrupt Clear Register ................................................................ 12-13
12.3.2.10 Status Register ........................................................................... 12-14
13.2.1 LCD DMA FIFOs ................................................................................... 13-4
13.2.2 Pixel Serializer....................................................................................... 13-4
13.2.3 How Pixels are Stored in Memory ......................................................... 13-5
13.2.4 Palette RAM .......................................................................................... 13-6
13.2.5 Grayscale Algorithm .............................................................................. 13-7
13.2.6 LCD Panel Resolutions ......................................................................... 13-7
13.3.1 CLCDC Register Summary ................................................................. 13-10
13.3.2 CLCDC Register Definitions ................................................................ 13-11
LH75400/01/10/11 (Preliminary) User's Guide
6/17/03
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