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Static Memory Controller
7.2 SMC Theory of Operation
After power-up, the SoC provides a single-chip select (nCS0) and 16 address bits
(A[15:0]). The SoC can be reprogrammed to exchange GPIO for up to three more chip
selects (nCS3 to nCS1) and up to eight more address bits (A[23:16]). The data port
defaults to 16 bits (boot ×16) after Reset. However, it can be set to 8 bits after reset by
setting the boot × 8 option. This can be expanded by reducing the number of GPIO avail-
able. See Chapter 21 for more details.
From an external perspective, the external memory bus cycle starts with the assertion of
nCSx and ends when nCSx is de-asserted. The following sections describe the internal
operations of the SMC.
7.2.1 SMC Write Process
The SMC has the same write control for all devices connected to it. Figure 7-1 shows a
write bus cycle. The following steps describe the write process.
1.
The SMC detects that an AHB bus cycle contains a transaction for it.
2.
The AHB bus transaction information informs the SMC that it is a write transaction.
The AHB bus transaction also contains the address of the transaction (all AHB bus
transactions are memory-mapped).
The SMC does not rely on asynchronously controlled timing of signals to ensure cor-
rect operation of the external memories. Rather, timing relationships are ensured by
timing the interface signals with the System Clock signal. This approach makes the tim-
ing characteristics of the interface dependent on the clock rates used.
3.
The SMC immediately places address bits [23:0] on the external A[23:0] address bus.
At the same time, it receives the write data from the AHB. (Being a pipelined bus, the
AHB presents the data on the clock after the transaction is started and the address is
presented.)
4.
On the next clock, the SMC asserts the appropriate nCSx signal, nBLEx signal (byte
lane enable), and the Write Enable signal (nWEN). It also presents the data to be writ-
ten to the SRAM on D[15:0].
The SMC supports 1 to 32 wait states. It also supports an nWAIT input that can be
used by an external device to vary the wait time.
5.
The system clock edge following the one during which the nCSx signal is asserted
counts as the end of the first wait state. If there are N wait states programmed for this
bank of memory, the SMC will hold this state for either N system clocks or until nWAIT
is sampled as being inactive on an system clock edge — whichever happens last.
6.
The nCSx signal and the nBLEx (byte lane enables) are removed during the following
system clock cycle.
7.
The A[23:0], D[15:0], and nCSx signals are removed on the following clock. The sys-
tem AHB is not held during the write. Up to 4 writes can be buffered in the SMC for
future execution.
7-2
LH75400/01/10/11 (Preliminary) User's Guide
6/17/03
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