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Timers
BITS
8:7
6:5
4:2
1
0
15-26
Table 15-31. CTRL Register Definitions (Cont'd)
FIELD
NAME
Input Edge Select Selects the rising edge, falling edge, both edges, or ignores
all changes of the input signal that is used as the capture trigger.
00 = Capture input CTCAP2B is ignored.
CAP1
01 = Rising edge of CTCAP2B.
10 = Falling edge of CTCAP2B.
11 = Both edges of CTCAP2B.
Input Edge Select Selects the rising edge, falling edge, both edges, or ignores
all changes of the input signal that is used as the capture trigger.
00 = Capture input CTCAP2A is ignored.
CAP0
01 = Rising edge of CTCAP2A.
10 = Falling edge of CTCAP2A.
11 = Both edges of CTCAP2A.
Count Clock Select
000 = System clock/2
001 = System clock/4
010 = System clock/8
011 = System clock/16
SEL
100 = System clock/32
101 = System clock/64
110 = System clock/128
111 = CTCLK
The CS field (bit [1]) must be clear for changes to the SEL field to take effect.
Start/Stop Counter 2
CS
0 = Stop Counter 2.
1 = Start Counter 2.
Counter 2 Clear Write a 1 to clear the contents of Timer 2 to 0x0000. Write
CCL
operations of 0 are ignored. This bit always reads 0 and is reset to 0 as the
counter is cleared.
LH75400/01/10/11 (Preliminary) User's Guide
DESCRIPTION
6/17/03
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