Interrupt Masking/Enabling Register; Table 23-9. Im Register; Table 23-10. Im Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

23.3.2.4 Interrupt Masking/Enabling Register

IM is the Interrupt Masking/Enabling Register. The active bits used in this register are
Read/Write.
This register contains seven bits that enable the interrupts. Software can read the Interrupt
Status bits through the IS Register, even if corresponding mask bits are set in this register.
Clearing the mask bits clears the pin-level interrupts, but not the interrupt status. The
status bits are ANDed with the mask bits to create the pin-level interrupts.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 23-10. IM Register Definitions

BIT NAME
31:7 ///
6 INTEN
5 ///
4 BOMSK
3 PMSK
2 EOSMSK
1 FWMSK
0 FOMSK
Analog-to-Digital Converter/Brownout Detector

Table 23-9. IM Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
0 0 0 0
R R R R
0xFFFC3000 + 0x0C
DESCRIPTION
Reserved Read as zero.
Interrupt Enable
0 = Disables global interrupt.
1 = Enables global interrupt.
Reserved Unpredictable when read.
Brown-Out Interrupt Enable
0 = Disable
1 = Enable
Pen Interrupt Enable
0 = Disable
1 = Enable
End-of-Sequence Interrupt Enable
0 = Disable
1 = Enable
FIFO Watermark Interrupt Enable
0 = Disable
1 = Enable
FIFO Overrun Interrupt Enable
0 = Disable
1 = Enable
6/25/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
///
0 0 0 0 0
RW R RW RW RW
17 16
0 0
R R
1 0
0 0
RW RW
23-13